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MOSEL VITELIC
V53C365805A 3.3 VOLT 8M X 8 EDO PAGE MODE CMOS DYNAMIC RAM
V53C365805A
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. EDO Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
40
40 ns 20 ns 16 ns 69 ns
50
50 ns 25 ns 20 ns 84 ns
60
60 ns 30 ns 25 ns 104 ns
Features
s 8M x 8-bit organization s EDO Page Mode for a sustained data rate of 63 MHz s RAS access time: 40, 50, 60 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 32-pin 400 mil SOJ, and 32-pin 400 mil TSOP-II s Single +3.3 V 0.3 V Power Supply s TTL Interface
Description
The V53C365805A is a 8,388,608 x 8 bit highperformance CMOS dynamic random access memory. The V53C365805A offers Page mode operation. The V53C365805A has an asymmetric address, 12-bit row and 11-bit column. All inputs are TTL compatible. Page Mode operation allows random access up to 2048 x 8 bits, within a page, with cycle times as short as 16 ns. These features make the V53C365805A ideally suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating Temperature Range
0C to 70C
Package Outline K
*
Access Time (ns) 40
*
Power 60
*
T
*
50
*
Std.
*
Temperature Mark
Blank
V53C365805A Rev. 1.0 January 1998
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32 Pin Plastic SOJ /TSOP-II PIN CONFIGURATION Top View
VCC I/O1 I/O2 I/O3 I/O4 NC VCC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
316580500-02
V53C365805A
Pin Names
A0-A11 RAS Row, Column Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output +3.3V Supply 0V Supply No Connect
VSS I/O8 I/O7 I/O6 I/O5 VSS CAS OE NC A11 A10 A9 A8 A7 A6 VSS
CAS WE OE I/O1-I/O8 VCC VSS NC
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Operating temperature range ..................0 to 70 C Storage temperature range ............... -55 to 150 C Soldering temperature ..................................260 C Soldering time...................................................10 s Input/output voltage .... -0.5 to min (VCC+0.5, 4.6) V Power supply voltage ........................-0.5V to 4.6 V Power dissipation .......................................... 1.0 W Data out current (short circuit) ...................... 50 mA
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
V53C365805A
Capacitance*
TA = 25C, VCC = 3.3 V 0.3 V, VSS = 0 V, f = 1 Mhz
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Min. -- -- -- Max. 5 7 7 Unit pF pF pF
Absolute Maximum Ratings*
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
8M x 8
I/O1 I/O2 I/O8
Data In Buffer WE CAS 8
Data Out Buffer 8
OE
No. 2 Clock Generator
11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Column Address Buffers (11)
11
Column Decoder
Refresh Controller Sense Amplifier I/O Gating Refresh Counter (12) 12 12 Row Address Buffers (12) 12 Row Decoder 4096 Memory Array 4096 x 2048 x 8 2048 x8
8
RAS
No. 1 Clock Generator
316580500-03
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DC and Operating Characteristics (1, 2)
TA = 0C to 70C, VCC = 3.3 V 0.3 V, VSS = 0 V, unless otherwise specified.
Access Time V53C365805A Min.
-2
V53C365805A
Symbol
ILI ILO ICC1
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating
Typ.
Max.
2
Unit
mA mA mA
Test Conditions
VSS VIN VCC VSS VOUT VCC RAS, CAS at VIH tRC = tRC (min.)
Notes
-2
2
40 50 60
155 130 105 2
2, 3, 4
ICC2 ICC3
VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 40 50 60
mA
RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2, 4
155 130 105 70 60 50 500
mA
ICC4
VCC Supply Current, EDO Page Mode Operation
40 50 60
mA
Minimum Cycle
2, 3, 4
ICC5 ICC6
VCC Supply Current, CMOS Standby VCC Supply Current, during CAS-before-RAS Refresh 40 50 60
mA mA
RAS VCC - 0.2 V, CAS VCC - 0.2 V 2, 4
155 130 105 -0.3 2.0 0.8
VIL VIH VOL VOH VOL VOH
Input Low Voltage Input High Voltage Output Low Voltage (LVTTL) Output High Voltage (LVTTL) Output Low Voltage (LVCMOS) Output High Voltage (LVCMOS)
V
1 1 IOL = 2 mA IOH = -2 mA IOL = 100 mA IOH = -100 mA 1 1 1 1
VCC+0.3 V 0.4 V V 0.2 V V
2.4
VCC-0.2
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Truth Table
FUNCTION
Standby Read Early-Write Delayed-Write Read-Modify-Write EDO Page Mode Read 1st Cycle 2nd Cycle EDO Page Mode Early Write 1st Cycle 2nd Cycle EDO Page Mode RMW 1st Cycle 2nd Cycle RAS only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh READ WRITE
V53C365805A
RAS
H L L L L L L L L L L L H(R)L H(R)L L(R)H(R)L L(R)H(R)L
CAS
H(R)X L L L L H(R)L H(R)L H(R)L H(R)L H(R)L H(R)L H L L L L
WE
X H L H(R)L H(R)L H H L L H(R)L H(R)L X H L H L
OE
X L X H L(R)H L L X X L(R)H L(R)H X X X L X
ROW ADDR
X ROW ROW ROW ROW ROW N/A ROW N/A ROW N/A ROW X X ROW ROW
COL ADDR
X COL COL COL COL COL COL COL COL COL COL N/A N/A N/A COL COL
I/O1-I/O4
High Impedance Data Out Data In Data In Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance High Impedance Data Out Data In
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AC Characteristics (6,7,8)
TA = 0 to 70 C,VCC = 3.3 V0.3V
-40 # Symbol Parameter Min. Max. - 50 Min. Max.
V53C365805A
- 60 Min. Max. Unit Note
Common Parameters
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tRC tRAS tCAS tRP tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF Random read or write cycle time RAS pulse width CAS pulse width RAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for 4k-refresh 69 40 6 25 6 0 5 0 5 9 7 6 32 5 1 - - 100k 10k - - - - - - 30 20 - - - 50 64 84 50 8 30 8 0 7 0 7 11 9 8 40 5 1 - - 50 64 - 100k 10k - - - - - - 37 25 104 60 10 40 10 0 10 0 10 14 12 10 48 5 1 - - 100k 10k - - - - - - 45 30 - - - 50 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
17 18 19 20 21 22 23 24 25 26 27 28 29 30 tRAC tCAC tCAA tOEA tRAL tRCS tRCH tRRH tCLZ tOFF tOEZ tDZO tCDD tODD Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay - - - - 20 0 0 0 0 0 0 0 10 10 40 10 20 10 - - - - - 10 10 - - - - - - - 25 0 0 0 0 0 0 0 13 13 50 13 25 13 - - - - - 13 13 - - - - - - - 30 0 0 0 0 0 0 0 15 15 60 15 30 15 - - - - - 15 15 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 8 12 12 13 14 14 8, 9 8, 9 8,10 8
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AC Characteristics (6,7,8) (Continued)
TA = 0 to 70 C,VCC = 3.3 V0.3V
-40 # Symbol Parameter Min. Max. - 50 Min. Max.
V53C365805A
- 60 Min. Max. Unit Note
Write Cycle
31 32 33 34 35 36 37 tWCH tWP tWCS tRWL tCWL tDS tDH Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time 5 5 0 6 6 0 5 - - - - - - - 7 7 0 8 8 0 7 - - - - - - - 10 10 0 10 10 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15
Read-modify-Write Cycle
38 39 40 41 42 tRWC tRWD tCWD tAWD tOEH Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time 89 52 22 32 5 - - - - - 109 65 28 40 7 - - - - - 128 77 32 47 10 - - - - - ns ns ns ns ns 15 15 15
EDO Page Mode Cycle
43 44 45 46 47 48 49 50 tPC tCPA tRAS tRHPC tCOH tOEP tOEHC tWEZ EDO Page Mode cycle time Access time from CAS precharge RAS pulse width in EDO page mode CAS precharge to RAS Delay Output Data Hold Time OE Pulse Width OE Hold Time from CAS High Output Buffer Turn-off Delay from WE 16 - 40 25 5 5 5 0 - 22 200k - -- -- -- 10 20 - 50 30 5 5 5 0 - 28 200k - -- -- -- 13 24 - 60 35 5 5 5 0 - 34 200k - -- -- -- 15 ns ns ns ns ns ns ns ns 7
EDO Page Mode Read-Modify-Write Cycle
51 52 tPRWC tCPWD EDO page mode read-write cycle time CAS precharge to WE 42 32 - - 53 41 - - 63 49 - - ns ns
CAS before RAS Refresh Cycle
53 54 55 56 57 tCSR tCHR tRPC tWRP tWRH CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS 5 5 0 5 5 - - - - - 5 5 0 5 5 - - - - - 5 10 0 10 10 - - - - - ns ns ns ns ns
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AC Characteristics (6,7,8) (Continued)
TA = 0 to 70 C,VCC = 3.3 V0.3V
-40 # Symbol Parameter Min. Max. - 50 Min. Max.
V53C365805A
- 60 Min. Max. Unit Note
Test Mode Cycle
58 59 tWTS tWTH Write command setup time Write command hold time 5 5 - - 5 5 - - 5 5 - - ns ns 18 18
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Notes:
1) All voltages are referenced to VSS.
V53C365805A
VIH may overshoot to VCC + 0.2V for pulse widths of < 4ns with 3.3V. VIL may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. 2) 3) 4) 5) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a edo page mode cycle (tPC). An initial pause of 100 ms is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. AC measurements assume tT = 5 ns. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. Measured with the specified current load and 100 pF at VOH = 2.0 V and VOL = 0.8 V. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA. Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. Either tDZC or tDZO must be satisfied. Either tCDD or tODD must be satisfied. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain opencircuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in ReadModify-Write cycles. In a Test Mode Read Cycle, the value of tRAC, tCAA, tCAC and tCPA are delayed by 5 ns from the specified value. These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must be adjusted by 5 ns.
6) 7) 8) 9) 10) 11) 12) 13) 14) 15)
16) 17)
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Waveforms of Read Cycle
tRC (1) tRAS (2) VIH RAS VIL tCSH (13) tRCD (10) VIH CAS VIL tASR (6) VIH Address VIL Row tRAH (7) tRCS (22) VIH WE VIL tCAA (19) tOEA (20) Column tRCH (23) tRRH (24) Row tRSH (12) tCAS (3) tCRP (14) tRP (4)
V53C365805A
tRAD (11) tASC (8) tCAH (9)
tRAL (21) tASR (6)
VIH OE VIL tDZC tDZO (28)
tCDD tODD (30)
I/O (Inputs)
VIH VIL
tCAC (18) tOEZ (27) Valid Data Out tRAC (17)
tOFF (26)
I/O (Outputs)
VOH Hi Z VOL
tCLZ (25)
Hi Z
"H" or "L"
WL1
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Waveforms of Write Cycle (Early Write)
tRC (1) tRAS (2) VIH RAS VIL tCSH (13) tRCD (10) VIH CAS VIL tRAD (11) tASR (6) VIH Address Row VIL tRAH (7) VIH WE VIL tWCH (31) tRWL (34) VIH OE VIL tDH (37) tCWL (35) tWCS (33) tWP (32) Column tASC (8) tRAL (21) tCAH (9) tASR (6) tRSH (12) tCAS (3) tCRP (14) tRP (4)
V53C365805A
.
Row
tDS (36) I/O (Inputs) VIH
Valid Data In VIL
I/O (Outputs)
VOH
Hi Z
VOL
"H" or "L"
WL2
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Waveforms of Write Cycle (OE Controlled Write)
tRC (1) tRAS (2) VIH RAS VIL tCSH (13) tRCD (10) VIH CAS VIL tRAD (11) tASR (6) VIH Address Row VIL tCWL (35) tRAH (7) VIH WE VIL tOEH (42) VIH OE VIL tDZO (28) tDZC I/O (Inputs) VIH VIL tCLZ (25) tOEA (20) VOH I/O (Outputs) Hi-Z VOL Hi-Z tODD (30) tDH (37) tDS (36) tOEZ (27) Valid Data tRWL (34) tWP (32) Column tASC (8) tRAL (21) tCAH (9) tASR (6) tRSH (12) tCAS (3) tCSH (13) tRP (4)
V53C365805A
.
Row
"H" or "L"
WL3
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Waveforms of Read-Write (Read-Modify-Write) Cycle
tRWC (38) tRAS (2) VIH RAS VIL tCSH (13) tRCD (10) VIH CAS VIL tRAH (7) tASR (6) VIH Address VIL tRAD (11) tAWD(41) tCWD (40) tRWD (39) VIH WE VIL tCAA (19) tOEA (20) Row Column tCWL (35) tRWL (34) tWP (32) tASC (8) tCAH (9) tRSH (12) tCAS (3) tRP (4)
V53C365805A
tCRP (14)
tASR (6)
Row
tRCS (22) VIH OE VIL tDZO (28) tDZC I/O (Inputs) VIH VIL
tOEH (42)
tDS (36) tDH (37) Valid Data in tCLZ (25) tCAC (18) tODD (30) tOEZ (27)
I/O (Outputs)
VOH VOL tRAC (17)
"H" or "L"
Data Out
WL4
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Waveforms of EDO Page Mode Read Cycle
V53C365805A
tRAS (45) VIH RAS VIL tHPC tCRP (14) VIH CAS VIL tCSH (13) tASC (8) tASR (6) Address VIH Row VIL tRAD (11) Column 1 Column 2 Column N tRAH (7) tCAH (9) tASC (8) tCAH (9) tASC (8) tCAH (9) tCAS (3) tCP (5) tCAS (3) tRSH (12) tRCD (10) tRHPC (46)
tRP (4)
tCRP (14) tCAS (3)
tRAL (21)
tRRH (24) tRCS (22) VIH WE VIL tOES VOH OE VOL tRAC (17) tAA tCAC (18) tCLZ (25) I/O (Output) VIH VIL Data Out 1 Data Out 2 Data Out N tCOH (47) tCOH (47) tOEZ (27) tOEA (20) tCAC (18) tAA tCPA (44) tCAC (18) tAA tCPA (44) tOFF (26) tRCH (23)
WL5 "H" or "L"
V53C365805A Rev. 1.0 January 1998
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Waveforms of EDO Page Mode Read Cycle (OE Control)
V53C365805A
tRAS (45) VIH RAS VIL tHPC tCRP (14) VIH CAS VIL tCSH (13) tRAH (7) tASR (6) VIH Address VIL tRAD (11)
Row Column 1 Column 2 Column N
tRP (4)
tRCD (10)
tRHCP
tRSH (12) tCP (5) tCAS (3) tCAS (3)
tCRP (14)
tCAS (3)
tRAL (21) tCAH (9) tASC (8) tCAH (9) tASC (8) tCAH (9)
tASC (8)
tRRH (24) tRCS (22) VIH WE VIL tOES tCAC (18) tAA tCPA (44) tOEHC (49) VOH OE VOL tRAC (17) tAA tCAC (18) VIH VIL tCLZ (25)
Data Out 1 Data Out 2 Data Out N
tRCH (23)
tCAC (18) tAA tCPA (44) tOEHC (49) tOFF (26)
tOEA (20)
tOEA (20) tOEP (48) tOEZ (27) tOEP (48)
tOEA (20) tOEZ (27)
tOEZ (27)
I/O (Output)
WL6
"H" or "L"
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Waveforms of EDO Page Mode Read Cycle (WE Control)
V53C365805A
tRAS (45) VIH RAS VIL tHPC tCRP (14) VIH CAS VIL tCSH (13) tRAH (7) tASC (8)
Row
tRP (4)
tRCD (10)
tRHPC (46)
tRSH (12) tCP (5) tCAS (3) tCAS (3)
tCRP (14)
tCAS (3)
tRAL (21) tCAH (9) tASC (8) tCAH (9) tASC (8) tCAH (9)
tASR (6) Address VIH
Column 1
Column 2
Column N
VIL tRAD (11) tAA tAA tRRH (24) tRCS (22) VIH WE VIL tWP (32) tCAC (18) tOES VOH OE VOL tRAC (17) tAA tCAC (18) tCLZ (25)
Data Out 1 Data Out 2 Data Out N
tRCH (23) tRCH (23) tRCS (22) tRCS (22)
tRCH (23)
tWP (32) tCAC (18) tCPA (44) tOFF (26)
tCPA (44)
tOEA (20)
tOEZ (27) tWHZ tWHZ
I/O (Output)
VIH VIL
WL7
"H" or "L"
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Waveforms of EDO Page Mode Early Write Cycle
V53C365805A
tRAS (2) VIH RAS VIL tHPC tCRP (14) VIH CAS VIL tCSH (13) tRAH (7) tASR (6) Address VIH VIL
Row Addr
tRP (4)
tRCD (10)
tRHPC (46)
tRSH (12) tCP (5) tCAS (3) tCAS (3)
tCRP (14)
tCAS (3)
tRAL (21) tCAH (9) tASC (8) tCAH (9) tASC (8) tCAH (9)
tASC (8)
Column 1
Column 2
Column N
tRAD (11) tCWL (35) tWCS (33) tWCH (31) tWP (32) tWCS (33) tCWL (35) t tWCH (31) WCS (33) tWP (32)
tRWL (34) tCWL (35) tWCH (31) tWP (32)
VIH WE VIL
VOH OE VOL tDS (36) VIH I/O (Input)
Data In 1 Data In 2 Data In N
tDH (37)
tDS (36)
tDH (37)
tDS (36)
tDH (37)
VIL
"H" or "L"
WL8
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Waveforms of EDO Page Mode Late Write Cycle
V53C365805A
tRAS (2) VIH RAS VIL tHPC tCRP (14) VIH CAS VIL tCSH (13) tRAH (7) tASR (6) VIH Address VIL tRAD (11) tCWL (35) tCWL (35) tCWL (35) tRWL (34) tRCS (22) VIH WE VIL tWP (32) tWP (32) tWP (32) tRCS (22) tRCS (22)
Row Column 1 Column 2 Column N
tRP (4)
tRCD (10)
tRSH (12) tCP (5) tCAS (3) tCP (5) tCAS (3)
tCRP (14)
tCAS (3)
tRAL (21) tCAH (9) tASC (8) tCAH (9) tASC (8) tCAH (9)
tASC (8)
tOEH (42) VOH OE VOL tODD (30)
tOEH (42)
tOEH (42)
tODD (30)
tDS (36) tDH (37) tODD (30) I/O (Input) VIH VIL
Data In 1
tDS (36)
tDH (37)
tDS (36)
tDH (37)
Data In 2
Data In N
WL16
"H" or "L"
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Waveforms of EDO Page Mode Read-Modify-Write Cycle
MOSEL VITELIC
tRASP VIH RAS VIL tRCD (10) CAS VIH VIL tASR (6) Address VIH
Row Column Column Column Row
tCSH (13) tCP (5) tCAS (3) tRAD (11) tRAH (7) tCAH (9) tASC (8) tASC (8) tCAH (9)
tRP (4) tPRWC (51) tCAS (3) tRSH (12) tCAS (3) tCRP (14)
tCAH (9) tASC (8)
tRAL (21) tASR (6)
VIL tRCS (22) WE VIH VIL
tRWD (39) tCWD (40)
tCWL (35)
tCPWD (52) tCWD (40)
tCWL (35)
tCPWD (52) tCWD (40)
tRWL (34) tCWL (35)
tAWD(41) tAA tOEA (20)
tAWD(41) tWP (32) tOEA (20) tWP (32)
tAWD(41) tOEA (20) tWP (32)
19
OE I/O (Inputs)
WL17
VIH VIL tDZC VIH VIL tCAC (18) tRAC (17) tODD (30) tOEZ (27) tDZO (28) tCLZ
(25)
Data In
tCPA (44) tDZC tODD (30)
Data In
tCPA (44) tDZC tODD (30)
Data In
tCLZ (25) tOEH (42) tDH (37) tAA tOEZ (27) tOEH (42) tDH (37)
tCLZ (25) tOEH (42) tCAC (18) tAA tDH (37)
VOH I/O (Outputs) VOL
tDS (36)
Data Out Data Out
V53C365805A
tDS (36)
Data Out
tDS (36)
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Early Write)
tRC (1) tRP (4)
VIH
V53C365805A
tRC (1) tRAS (2) tRP (4)
tRAS (2)
RAS
VIL
tRCD (10)
VIH
tRSH (12)
tCHR (54)
tCRP (14)
CAS
VIL
tRAD (11) tRAH (7) tASR (6) tASC (8) tCAH (9) Column tWRP (56) tWRH (57) tASR (6)
VIH
Address
VIL
Row tWCS (33)
Row
tWCH (31)
VIH
tWP (32)
WE
VIL
tDS (36)
VIH
tDH (37)
I/O (Input)
Valid Data
VIL
I/O (Output)
VOH
HI-Z
VOL
"H" or "L"
WL12
V53C365805A Rev. 1.0 January 1998
20
MOSEL VITELIC
Waveforms of Test Mode Entry Cycle
tRC (1) tRP (4)
VIH
V53C365805A
tRAS (2)
tRP (4)
RAS
VIL
tRPC (55) tCSR (53) tCP (5) tCHR (54) tRPC (55) tCRP (14)
VIH
CAS
VIL
tASR (6)
tRAH (7)
VIH
Address
VIL
Row
tWTS (58)
VIH
tWTH (59)
WE
VIL
VIH
OE
VIL
tODD (30) I/O (Inputs)
VIH HI-Z VIL
tCDD (29)
tOEZ (27) I/O (Outputs)
VOH
HI-Z
VOL
tOFF (26)
"H" or "L"
WL15
V53C365805A Rev. 1.0 January 1998
21
MOSEL VITELIC
Package Diagrams
32-pin 400 mil SOJ
0.138 0.009 [3.51 0.250] 0.019 [0.5] 0.031 [0.8] min. 30 0.400 0.009 [10.16 0.13*]
V53C365805A
0.007 0.004 [0.2 0.1]
0.05 [1.27] 0.20 -0.005 [0.51-0.130] 32
0.007 [0.18] M 32x
0.032 max. [0.81 max.] 17
0.370 0.009 [9.4 0.25]
0.004 [0.1] 0.007 [0.18] M
0.440 0.005 [11.18 0.13]
1 0.830 0.009 [21.08 0.25*] Index Marking
16
Units in inches [mm]
* Does not include plastic or metal protrusion of 0.15 max. per side
32-pin 400 mil TSOP-II
0.039 0.002 [1 0.05] 0.0040.002 [0.10.05] 0.047 Max [1.2 Max] 0.4 0.005 [10.16 0.13] 0.006 -0.001
+0.08 0.15 -0.03 +0.003
0.050 [1.27] 0.016 +0.002 -0.004 0.4 +0.05 -0.1 32 17 0.008 [0.2] M 32x
0.004 [0.1]
0.0200.004 [0.5 0.1] 0.4630.008 [11.76 0.2]
1 0.8250.005 [20.950.13]
1
16
1
Unit in inches [mm]
Does not include plastic or metal protrusion of 0.010 [0.25] max. per side
V53C365805A Rev. 1.0 January 1998
22
MOSEL VITELIC
Notes:
V53C365805A
V53C365805A Rev. 1.0 January 1998
23
MOSEL VITELIC
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-578-3344 FAX: 886-3-579-2838
V53C365805A
GERMANY (CONTINENTAL EUROPE & ISRAEL )
71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
JAPAN
WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 81-43-299-6000 FAX: 81-43-299-6555
HONG KONG
19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2665-4883 FAX: 852-2664-7535
IRELAND & UK
BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185
SOUTHWESTERN
SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174
CENTRAL & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341
NORTHEASTERN
SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347
(c) Copyright 1997, MOSEL VITELIC Inc.
2/99 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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